1. Field of the Invention
The present invention relates to a thermal head driving integrated circuit (hereinunder referred to as "IC") and a thermal head driving circuit incorporating the same.
2. Description of the Related Art
Various printing machines such as a thermal printer or a facsimile machine for printing by heat are conventionally known. Such a machine is provided with a thermal head having a plurality of resistors for generating heat arranged in parallel. The resistors are heated when electric current is supplied to them. It is therefore possible to selectively heat a predetermined number of resistors by selectively supplying the current to the resistors. When a letter or the like is printed by using the thermal head, the resistors are heated under control in accordance with the shape of the letter or the like being printed.
The circuit for controlling the heating operation of the resistors, namely the thermal head driving circuit, is generally constituted by a thermal head driving IC. FIG. 11 shows the internal circuit of an example of a conventional thermal head driving IC.
The IC shown in FIG. 11 is provided with driving output terminals DO1 to DO64 which are connected to the corresponding resistors. In other words, the IC has a driving output of 64 bits. The data for controlling the output from the driving output terminals DO1 to DO64 to the resistors are serially input to the IC. For this purpose, the IC has a serial data input terminal SI.
The IC includes a shift register 10, latches for 64 bits 12, AND gates for 64 bits 14 and transistors for 64 bits 16. The shift register 10 is composed of, for example, 64 cascaded D flip-flops (not shown). The shift register 10 shifts the serial data input from the serial data input terminal SI in series in accordance with the clock and converts them into parallel data of 64 bits. The clock is input from a clock signal input terminal CLK. The symbol SO represents a serial data output terminal which is used when a plurality of the ICs shown in FIG. 11 are connected in cascade.
Each of the latches 12 latches the corresponding 1 bit from the parallel output supplied from the shift register 10 in accordance with the latch signal. The latch signal is input from a latch signal terminal LAT/LAT to each latch 12 through the exclusive OR (hereinunder referred to as "EOR") gate 18 which is formed within the IC.
One input of the EOR gate 18 is connected to the latch signal terminal LAT/LAT, and the other input is pulled down within the IC and is connected to a control signal terminal CTL. It is therefore possible to determine whether each latch 12 should latch data in accordance with a positive latch signal LAT (what is called positive logical latch) or a negative latch signal LAT (what is called negative logical latch) by controlling the potential of the control signal terminal CTL by a control signal supplied from an external device to the IC.
The data latched by the latches 12 are input to the AND gates 14. To one terminal of each three-input AND gate 14, the corresponding bit is input from a latch 12. Strobe signals are input to the other two of input terminals. One of these input terminals is connected to a strobe signal terminal AEO through an inverter 20 and is pulled up within the IC. The other input terminal is connected to a strobe signal terminal BEO through a buffer 22 and is pulled down within the IC. By fixing the potential of either the strobe signal terminal AEO or the strobe signal terminal BEO and inputting a strobe signal from the other terminal, the user can select a low-level active mode or a high-level active mode.
The transistors 16 consist of 64 field-effect transistors (FETs). Alternatively, the transistors 16 may consist of bipolar transistors. The output terminal of each AND gate 14 is connected to the gate of the corresponding FET 16. The source and drain of each FET 16 are connected to the corresponding driving output terminal from DO1 to DO64 or the grounding terminals GND and GND2, respectively. In the case of using the IC shown in FIG. 11 for a thermal printer or the like, resistors (not shown) are connected between the driving output terminals DO1 to DO64 and the grounding terminals GND and GND2. An output voltage VH is applied to the resistors from a power source (not shown).
When a printing operation is carried out using this IC, data are first input serially from the serial data input terminal SI. The shift register 10 converts the data into parallel data. The parallel data obtained are latched by the latches 12 and output to the transistors 16 through the AND gates 14 as gate signals. The transistors 16 are selectively turned ON/OFF in accordance with the corresponding bits of the parallel data, and the voltage VH is selectively applied to the 64 resistors in accordance with the ON/OFF state of the transistors. In other words, the 64 resistors are selectively heated. Since the heating time is determined by the time during which the strobe signal is generated, the quantity of heat is controlled by the time during which the strobe signal is generated. In addition, since the latches 12 are inserted between the shift register 10 and the AND gates 14, the operation of inputting serial data to the IC and the operation of heating the resistors can be executed in parallel. High-speed operation is therefore possible.
The IC is provided with the serial data output terminal SO, so that it is possible to use a plurality of ICs as one block. For example, if the serial data output terminal SO of a first IC is connected to the serial data input terminal SI of a second IC, a block of outputs of 128 bits is composed.
In order to increase the printing speed, thermal heads are conventionally divided into a plurality of blocks and the printing operation is controlled in each block, thereby enabling parallel operation. In this case, the same number of strobe signals as the number of blocks are used. However, printing machines have recently demanded a reduction in the size of the IC and the circuit incorporating the IC while maintaining or enhancing the high-speed printing capacity. In the structure shown in FIG. 11, the latch group 12 is a hindrance to the reduction in the size of the IC and a circuit incorporating the IC. In addition, in the case of printing in blocks separately from each other by using a plurality of strobe signals, the external interface circuit becomes complicated.